1. Field of the Invention
The invention relates to a dynamic random access memory (DRAM), and more particularly, to an access and operating method of a DRAM for reducing address numbers thereof.
2. Description of the Related Art
A dynamic random access memory (DRAM) has existed for several years. The dramatic increase in storage capacity thereof, has been achieved via advances in semiconductor fabrication technology and circuit design technology. Considerable advances have also resulted in higher and higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
Modern DRAM semiconductor memories require more area on semiconductor chips, despite the fact that structures for the rapidly increasing memory capacities are becoming smaller, and the memory cell fields thereof are becoming larger. The area requirement is associated with considerable production costs. Apart from the memory cell fields, a significant proportion of the area of a semiconductor memory chip is occupied by control, address and data lines, some of which are disposed alongside the memory cell fields and are becoming wider with the increasing memory capacity of the semiconductor memory, and by control devices which are required for operation of the data memory.
A DRAM receives a plurality of input signals from a controller, wherein the input signals define parameters such as the location, or address, of the memory data and transmit the memory data. A read or write transaction with a DRAM generally involves two steps. First, address (e.g. row address and column address) and control signals are transmitted to the DRAM, allowing the DRAM to prepare for the data transfer. Second, the DRAM reads or writes the data, completing the data transfer. However, for the controller, pins corresponding to the control, address and data lines also occupy a larger area. In general, the controller is implemented in an integrated circuit (IC). Therefore, a pad limitation problem of the IC often occurs, so that the size of the IC can not be minimized.